offalobbyProjects

FPGA & Verilog Projects

A 16-bit Verilog RTL processor and a set of Spartan-7 FPGA designs: a logic unit, a 7-segment decoder and a dual-alarm clock.

When
Fall 2026
Where
Rice University
Tools
  • Verilog
  • Xilinx Vivado
  • Icarus Verilog
  • Spartan-7 FPGA

Developed a 16-bit Verilog RTL processor (8-register ISA, ALU, instruction decoder, conditional branching) and Spartan-7 FPGA designs (logic unit, 7-segment decoder, dual-alarm clock), using Vivado, Icarus Verilog testbenches, finite-state machines and clock-enable logic, with the processor integrated on the FPGA.

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