Pipelined CPU Microarchitecture & SystemVerilog Verification
A 5-stage pipelined processor in Verilog/SystemVerilog with hazard detection, forwarding and branch control, verified by automated regression tests.
- When
- Feb – Aug 2026
- Where
- Personal
- Tools
- Verilog
- SystemVerilog
- FPGA
Designed and verified a 5-stage pipelined processor in Verilog/SystemVerilog, implementing hazard detection, forwarding, and branch control with automated regression testing and FPGA timing analysis.